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| F72568 Advanced ACPI Controller IC Datasheet Release Date: July, 2007 Version: 0.25P Fintek Feature Integration Technology Inc. F72568 F72568 Datasheet Revision History Version 0.20P 0.21P 0.22P 0.23P 0.24P 0.25P Date Nov.2005 2005/12/20 2006/9 2006/10 2007/3 2007/7 Page Preliminary version 1 4 20 15 20 19 Added schematic Revision History Correct the description relative to Vref Correct pin description, PIN 16 Application circuit updated PLED, SLED register description Application circuit updated Update company address Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. 1 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 Table of Contents 1 2 3 4 5 6 GENERAL DESCRIPTION ........................................................................................................................................................ 1 FEATURE ..................................................................................................................................................................................... 1 PIN CONFIGURATION & BLOCK DIAGRAM...................................................................................................................... 2 SIMPLIFIED POWER SYSTEM DIAGRAM .......................................................................................................................... 3 PIN DESCRIPTION..................................................................................................................................................................... 3 FUNCTIONAL DESCRIPTION ................................................................................................................................................. 7 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 ACPI STATE .............................................................................................................................................................................. 7 CHARGE PUMP .......................................................................................................................................................................... 7 SOFT-START .............................................................................................................................................................................. 8 REFERENCE VOLTAGE ............................................................................................................................................................... 8 UNDER VOLTAGE PROTECTION................................................................................................................................................. 8 OVER CURRENT PROTECTION................................................................................................................................................... 8 ACCESS INTERFACE .................................................................................................................................................................. 9 REGISTER DESCRIPTION. .................................................................................................................................................... 10 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 REGISTER INDEX 01H......................................................................................................................................................... 10 PWM_VRAM_11, PWM_VRAM_10 FINE TUNE VOLTAGE REGISTER INDEX 02H .......................................................... 10 REGISTER INDEX 03H......................................................................................................................................................... 11 PWM_VTT_10, PWM_VTT_11 FINE TUNE VOLTAGE REGISTER INDEX 04H................................................................... 11 REGISTER INDEX 05H......................................................................................................................................................... 11 LR_PCIE_10, LR_PCIE_11 FINE TUNE VOLTAGE REGISTER INDEX 06H.......................................................................... 12 REGISTER INDEX 07H......................................................................................................................................................... 12 LR3_10, LR3_11 FINE TUNE VOLTAGE REGISTER INDEX 08H........................................................................................... 13 LRPCIE_11, LR3_11 FINE TUNE VOLTAGE REGISTER INDEX 09H .................................................................................... 13 7.10 PLED ACPI FREQUENCY SETTING REGISTER INDEX 0AH ................................................................................................. 14 7.11 PLED ACPI FREQUENCY SETTING REGISTER INDEX 0BH ................................................................................................. 15 7.12 SLED ACPI FREQUENCY SETTING REGISTER INDEX 0CH ................................................................................................. 15 7.13 UNDER VOLTAGE, OVER CURRENT ENABLE PROTECTION REGISTER INDEX 10H............................................................... 15 7.14 REGISTER INDEX 11H......................................................................................................................................................... 16 8 9 ELECTRICAL CHARACTERISTIC....................................................................................................................................... 17 ORDERING INFORMATION .................................................................................................................................................. 18 2 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 10 PACKAGE DIMENSIONS (48LQFP)...................................................................................................................................... 19 11 APPLICATION CIRCUIT ........................................................................................................................................................ 20 3 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 1 General Description The F72568 is a fully compliant ACPI controller IC specific for Intel CPU platform. Used with an ATX power supply, this chip integrates synchronous PWM controller and regulator, several linear controllers, switching signals, monitoring and control function into 48 pin LQFP package. Its operation mode (sleep or active) is selectable through some control signals. The F72568 provides 3 switching signals which can generate 5VDUAL, 5VUSB & 3.3VDUAL etc. The F72568 can also provide 6 linear controllers including VCCVID output with power good signal. This chip integrates a charge pump engine to provide higher driving voltage for appropriate gate during standby. On the other hand, this chip offers current limiting that protect each PWM outputs, and provides soft-start for linear controller to avoid rush current. The power LED is programmable and compliant with PC2001. Moreover, this high-performance chip integrates I2C interface to adjust VRAM, VTT, LR_PCIE, and LR_3 output. This chip is in 48pin LQFP package and powered by 5VSB. 2 Feature ACPI compliant sleep state control Provide 3 switching controlled signals for 5VDUAL, 5VUSB and 3.3VDUAL Programmable 5VDUAL/5VSTR/5VCC for USB device wake up Provide 6 linear controller and typically use for - -- 1 channel for Dual power -- 1 channel for PCI_E power -- 3 channels for 0.8~5V voltage requirement -- 1.2V VCCVID with VID_GD signal output Provide one PWM controller for DDR VDDQ Provide one PWM regulator for CPU/GMCH VTT termination 1 PWROK input signal(typically from ATXPWOKIN) and 1 PWROK output signal Provide resume reset signal(RSMRST#) Programmable power LED control Provide VREF and VSB9V voltage for generating different voltage use Power up soft-start and under-voltage monitoring for the linear regulators Over current protection(OCP) on both PWM controller and regulator Integrate I2C interface Provide VREF/1.25V 48 pin LQFP package and 5VSB operation 1 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 3 Pin Configuration & Block Diagram PLED SLED S5# SS 1.25VREF SCLK SDATA VSB5V VCC3V VTT_PWM VTT_COMP VTT_OPS VTT_FB VRAM_UGATE VRAM_LGATE VRAM_OPS VRAM_FB LR1_DRV LR1_SEN LR2_DRV LR2_SEN LR3_DRV LR3_SEN PWOK PWOKIN FAULT# TURBO# PS_ONIN# VID_GD RSMRST# VCCGATE USBGATE DUALGATE DUAL3V_DRV DUAL3V_SEN VREF Control Logic I2C Interface VTT PWM Regulator VRAM PWM Controller 5VDUAL 5VUSB 3VDUAL LR Controller VPCIE LR Controller VID LR Controller F72568 Linear Controller 1 Linear Controller 2 VPCIE_DRV VPCIE_SEN Charge Pump Linear Controller 3 GND VBAT VID_DRV VID_SEN CP C1 C2 2 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 4 Simplified Power System Diagram 12V Multi-Phase PWM VID_GD MOSFET Driver Intel CPU (5VDUAL) VID_PWR VRAM_UGATE VDDQ VRAM_LGATE DRAM 5VSB 3V Fintek F72568DG VTT_PWM MOSFET Driver VGMCH GMCH (NB) PCIE x 16 5V PCIE_PWR(1.5V) VREF LR1~3 ICH (SB) USB Device Other Device PCIE x 1 ATX Power 5VDUAL 5VUSB 3VDUAL 5 Pin Description I/OD12ts OUT5 OD12 OD16 OD24 INts AIN AOUT P - TTL level bi-directional pin. Open-drain schmitt trigger output with 16 mA sink capability - Output pin with 5 mA source-sink capability - Open-drain output pin with 12 mA sink capability - Open-drain output pin with 16 mA sink capability - Open-drain output pin with 24 mA sink capability - TTL level input pin and schmitt trigger - Input pin(Analog) - Output pin(Analog) - Power 3 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 Power Pins PIN NO 10 19 30 32 42 44 46 PIN NAME VSB5V GND GND VSB5V GND VBAT VCC3V VRAM_UGATE and VRAM_LGATE signal power, commend to connect to 16 VCC_PWM 12Vcc P Power pins TYPE DESCRIPTION Reset & Power Good & Control signal PIN NO 48 1 2 3 9 43 45 47 PIN NAME FAULT# PWOKIN PS_ONIN# S5# VID_GD RSMRST# PWOK TURBO# TYPE PWR VCC3V VSB5V VSB5V VSB5V VSB5V VBAT VBAT VCC3V Error input signal for power off. Power Good Schmitt Trigger input signal. Typically connected to ATX power good. Normal power control signal input. A low active ACPI control signal governing the S5 state. Typically connected to chipset S5# signal. This pin is the open drain output of the VCCVID power good comparator. As VSB come in, this pin will generate RSMRST# signal output which is delayed 66ms as VSB arrives at 3.3V Power Good output signal. Enable adjustable power signal. DESCRIPTION INts INts INts INts OD12 OD12 OD16 INts Switching Signal & Linear/PWM Controller PIN NO 11 12 13 14 15 17 18 20 21 PIN NAME VTT_PWM VTT_FB COMP VRAM_FB VRAM_OPS VRAM_LGATE VRAM_UGATE VTT_OPS VID_DRV TYPE PWR VSB5V VSB5V VSB5V VSB5V VSB5V VCC_PWM VCC_PWM VSB9V VSB9V DESCRIPTION External buffer PWM control output signal External buffer PWM feedback signal OUT5 AIN AOUT AIN AOUT/AIN AOUT AOUT AOUT/AIN AOUT Output of the error amplifier used to compensate the feedback loop of the PWM controller. VRAM PWM feedback signal VRAM PWM current protection signal VRAM PWM low gate control signal VRAM PWM up gate control signal External buffer PWM current protection signal Connect this pin to the gate of a suitable N-channel MOSFET. VID_SEN and VID_DRV act as a linear regulator and generate voltage 4 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 for S0 state power. 22 VID_SEN AIN VSB5V Sense the voltage of linear regulator. VID_SEN and VID_DRV act as a linear regulator and generate voltage for S0 state power. Sense the voltage of linear regulator. LR3_SEN and LR3_DRV act as a 24 LR3_SEN AIN VSB5V linear regulator and generate voltage for standby or STR power. Default for standby power. If VIN is main power, it can generate voltage for S0 sate power. Connect this pin to the gate of a suitable N-channel MOSFET. 25 LR3_DRV AOUT VSB9V LR3_SEN and LR3_DRV act as a linear regulator and generate voltage for standby or STR power. Default for standby power. If VIN is main power, it can generate voltage for S0 sate power. Connect this pin to the gate of a suitable N-channel MOSFET. 26 LR2_DRV AOUT VSB9V LR2_SEN and LR2_DRV act as a linear regulator and generate voltage for standby or STR power. Default for standby power. If VIN is main power, it can generate voltage for S0 sate power. Sense the voltage of linear regulator. LR2_SEN and LR2_DRV act as a 27 LR2_SEN AIN VSB5V linear regulator and generate voltage for standby or STR power. Default for standby power. If VIN is main power, it can generate voltage for S0 sate power. Sense the voltage of linear regulator. LR1_SEN and LR1_DRV act as a 33 LR1_SEN AIN VSB5V linear regulator and generate voltage for standby or STR power. Default for standby power. If VIN is main power, it can generate voltage for S0 sate power. Connect this pin to the gate of a suitable N-channel MOSFET. 34 LR1_DRV AOUT VSB9V LR1_SEN and LR1_DRV act as a linear regulator and generate voltage for standby or STR power. Default for standby power. If VIN is main power, it can generate voltage for S0 sate power. Connect this pin to the gate of a suitable N-channel MOSFET. 35 VPCIE_DRV AOUT VSB9V VPCIE_SEN and VPCIE_DRV act as A linear regulator and generate voltage for S0 state power. 36 VPCIE_SEN AIN VSB5V Sense the voltage of linear regulator. VPCIE_SEN and VPCIE_DRV act as a linear regulator and generate voltage for S0 state power. Sense 37 DAUL3V_SEN AIN VSB5V the voltage of linear regulator. VDUAL3V_SEN and VDUAL3V_DRV act as an adjustable linear regulator and this regulator is typically incorporated with VCCGATE to generate dual voltage. Connect this pin to the gate of a suitable N-channel MOSFET. 38 DUAL3V_DRV AOUT VSB9V VDUAL3V_SEN and VDUAL3V_DRV act as an adjustable linear regulator and this regulator is typically incorporated with VCCGATE to generate dual voltage. Connect this pin to the gate of a suitable N-channel MOSFET. This 39 VCCGATE AOUT VSB9V pin is incorporated with pin38 and 39 (DUAL3V_DRV+DUAL3V_SEN) to generate dual 3.3V voltage. Besides, this pin can be incorporated with pin41 (USBGATE) to generate USB voltage. Incorporated with pin 42 (DUALGATE) to generate dual 5V voltage. 40 USBGATE AOUT VSB9V Connect this pin to the gate of a suitable N-channel MOSFET. 5 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 Incorporated with pin 40 (VCCGATE) to generate USB voltage. 41 DUALGATE AOUT VSB9V Connect this pin to the gate of a suitable N-channel MOSFET. Incorporated with pin 40 (VCCGATE) to generate dual 5V voltage. Charge Pump PIN NO 28 29 31 PIN NAME CP C2 C1 TYPE PWR VSB9V capacitor. VSB9V power output. VSB9V VSB5V between C1 and C2 Positive end of charge pump capacitor Negative end of charge pump capacitor. Connect a 1uF ceramic capacitor AOUT DESCRIPTION Charge pump output (9V nominal). Decouple this pin with 1uF ceramic P AOUT Power LED PIN NO 6 7 PIN NAME PLED SLED TYPE PWR VSB5V VSB5V DESCRIPTION Power LED. Can be programmed by setting register Suspend LED. Can be programmed by setting register OD24 OD24 Others PIN NO 4 5 8 23 PIN NAME SCLK SDATA VREF SS TYPE PWR VSB5V VSB5V VSB5V VSB5V soft-start rate. The value of capacitor is bigger, the slew rate is slower. 2 DESCRIPTION I C serial bus clock (Address 5Eh) I C serial bus data Provide 1.25V reference voltage Soft-Start. Connect this pin to a small ceramic capacitor to determine the 2 INts I/OD12ts AOUT AIN 6 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 6 Functional Description 6.1 ACPI state The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use of power in a computer. It lets computer manufacturer and user to determine the computer's power usage dynamically. There are three ACPI states that are of primary concern to the system designer and they are designated S0, S3 and S5. S0 is a full-power state and in this state, the computer is being actively used. The other two are called sleep states and reflect different power consumption when power-down. S3 is a state the processor is powered down but the last state is being stored in memory which is still active. S5 is a state that memory is off and the last state of the processor has been stored to the hard disk. Take S3 and S5 as comparison, since memory is fast, the computer can quickly come back to full-power state. But the disk is slower than the memory, the computer takes longer time to come back to full-power state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3. It is anticipated that only the following state transitions may happen: S0S3, S0S5, S5S0, S3S0 and S3S5. Among them, S3S5 is illegal transition and won't be allowed by state machine. In order to get to S5 from S3, it is necessary to enter S0 first. As for transition S5S3 will occur only as an immediate state during state transition from S5S0. It isn't allowed in the normal state transition. 6.2 Charge pump The F72568 incorporated with an embedded charge pump to provide higher driving voltage. Pin 29(CP) supports 10mA driving current and ensures 9V output voltage or above. In main operation, the VSB9V signals of F72568 are run from the +12V supplied by ATX power which also supplies to other MOSFET gates. However, during standby state, the +12V will be off and it needs to provide power to the chip and the appropriate gates. Therefore F72568 incorporated with a free running charge pump. As shown in schematic, there is a capacitor connected between C1 and C2 of the F72568 acts as a charge pump with internal diodes. The 12V input must has a serial diode to prevent back-feeding the charge pump to the +12V main when in standby. It also needs a bypass capacitor connected with 12V input line to filter high-frequency noise. 7 2007 V0.25P Fintek 6.3 Soft-start Feature Integration Technology Inc. F72568 SS of the F72568 acts as soft-start function. As shown in schematic, a ceramic capacitor is attached between this pin and ground. When power is first applied to the chip, a constant current is applied from the pin into an external capacitor, linearly ramping up the voltage. This ramp in turn controls the internal reference of F72568 providing a soft-start for linear controller. As for switches, they must be either on or off in the system therefore soft-start has no effect on them. It is important to know soft-start is not an enable signal; pulling it low will not be sure to turn off all outputs. But if there are appropriate signals asserted, the switches will be turn on at once. The actual state of F72568 on power up will be determined by the controlled input signal. And the soft-start is effective only during power on. 6.4 Reference voltage The pin9 (VREF) is an output pin that is driven by a small output buffer to provide the 1.25V reference voltage to other devices in the system. 6.5 Under Voltage Protection If the FB voltage drops below 0.5V, a fault signal is generated. When under voltage condition occurs, the related linear controller will shut down. 6.6 Over Current Protection Sense the low-side MOSFET's RDS (ON) to set over-current trip point. Connect a resistor (ROCSET) from this pin to the PHASE to set the over-current trip point. ROCSET, an internal 40A current source, and the lower MOSFET on resistance, RDS (ON), set the converter over-current trip point (IOCSET) according to the following equation: If over current occurs, the F72568 will shut down the PWM 8 2007 V0.25P Fintek 6.7 Access Interface Feature Integration Technology Inc. F72568 The F72568 can be connected to a compatible 2-wire serial system Management Bus (SMBus) as a slave device under the control of the master device, using two device terminals SCLK and SDATA. The controller can provide a clock signal to the device SCLK pin and read/write data from/to the device through the device SDATA pin. The address default is 0x5E(0101_1110) and the operation of device to the bus is described with details in the following sections. (a) SMBus write to internal address register followed by the data byte 0 SCLK SDATA Start By Master 7 8 0 7 8 0 1 0 1 1 1 1 R/W Ack by 568 D7 D6 D5 D4 D3 D2 D1 D0 Ack by 568 Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte 7 SCLK (Continued) SDATA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 8 Frame 3 Data Byte Stop by Master Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte (b) Serial bus write to internal address register only 0 SCLK SDATA Start By Master 7 8 0 7 8 0 1 0 1 1 1 1 R/W Ack by 568 D7 D6 D5 D4 D3 D2 D1 D0 Ack by 568 Stop by Master Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte Figure 2. Serial Bus Write to Internal Address Register Only (c) Serial bus read from a register with the internal address register prefer to desired location 0 SCLK SDATA Start By Master 7 8 0 7 8 0 1 0 1 1 1 1 R/W Ack by 568 D7 D6 D5 D4 D3 D2 D1 D0 Ack Stop by by Master Master Frame 1 Serial Bus Address Byte 1 Frame 2 Internal Index Register Byte Figure 3. Serial Bus Read from Internal Address Register 9 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 7 Register Description. 7.1 Register Index 01h Reserved register. Do not write the reserced register to avoid the mis-action, please. 7.2 Bit PWM_VRAM_11, PWM_VRAM_10 Fine tune Voltage Register Index 02h Name R/W Default Description According to Turbo1hardware pin setting to fine tune PWM_VRAM reference voltage. If Turbo = 1, the PWM_VRAM Voltage table is set by Register 02h bit 7:4. 0000 : 0.74V 0001 : 0.76V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V 7:4 PWMVRAM_11 R/W 3 0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V The function must be enable by Register 09 Bit3 and Register 0A bit 3 According to Turbo hardware pin setting to fine tune PWM_VRAM reference voltage. If Turbo = 0, the PWM_VRAM Voltage table is set by Register 02h bit 3:0. 0000 : 0.74V 0001 : 0.76V 3:0 PWMVRAM_10 R/W 3 0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3 10 2007 V0.25P Fintek 7.3 Register Index 03h Feature Integration Technology Inc. F72568 Reserved register. Do not write the reserved register to avoid the mis-action, please. 7.4 PWM_VTT_10, PWM_VTT_11 Fine tune Voltage Register Index 04h Bit Name R/W Default Description According to Turbo hardware pin setting to fine tune PWM_VTT reference voltage. If Turbo = 1, the PWM_VTT Voltage table is set by Register 04h bit 7:4. 0000 : 0.74V 0001 : 0.76V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V 7:4 PWMVTT_11 R/W 3 0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V The function must be enable by Register 09 Bit3 and Register 0A bit 3 According to Turbo hardware pin setting to fine tune PWM_VTT reference voltage. If Turbo = 0, the PWM_VTT Voltage table is set by Register 04h bit 3:0 0000 : 0.74V 0001 : 0.76V 3:0 PWMVTT_10 R/W 3 0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3 7.5 Register Index 05h Reserved register. Do not write the reserved register to avoid the mis-action, please. 11 2007 V0.25P Fintek 7.6 Feature Integration Technology Inc. F72568 LR_PCIE_10, LR_PCIE_11 Fine tune Voltage Register Index 06h Bit Name R/W Default Description According to Turbo hardware pin setting to fine tune LR_PCIE reference voltage. If Turbo = 1, the LR_PCIE Voltage table is set by Register 06h bit 7:4. 0000 : 0.74V 0001 : 0.76V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V 7:4 LRPCIE_11 R/W 3 0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V The function must be enable by Register 09 Bit3 and Register 0A bit 3 According to Turbo hardware pin setting to fine tune LR_PCIE reference voltage. If Turbo = 0, the LR_PCIE Voltage table is set by Register 06h bit 3:0 0000 : 0.74V 0001 : 0.76V 3:0 LR_PCIE_10 R/W 3 0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3 7.7 Register Index 07h Reserved register. Do not write the reserved register to avoid the mis-action, please. 12 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 7.8 LR3_10, LR3_11 Fine tune Voltage Register Index 08h Bit Name R/W Default Description According to Turbo hardware pin setting to fine tune LRPCIE reference voltage. If Turbo = 1, the LRPCIE Voltage table is set by Register 08h bit 7:4. 0000 : 0.74V 0001 : 0.76V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V 7:4 LR3_11 R/W 3 0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V The function must be enable by Register 09 Bit3 and Register 0A bit 3 According to Turbo hardware pin setting to fine tune LR3 reference voltage. If Turbo =0, the LR3 Voltage table is set by Register 08h bit 3:0 0000 : 0.74V 0001 : 0.76V 0010 : 0.78V 3:0 LR3_10 R/W 3 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3 7.9 Bit 7-6 5 4 LRPCIE_11, LR3_11 Fine tune Voltage Register Index 09h Name USBMODE VRAM_MODE VTT_MODE R/W R/W R/W R/W Default 1 1 0 Description USB Power mode select, 00:DUAL 01:STR 10:OFF 11:OFF VRAM Power mode select, 0 : VCC 1:STR VTT Power mode select, 0 : VCC 1: STR 13 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 TURBO function Enable, if set to 1 the register 01~08h will enable fine 3 TURBO_EN R/W 0 tune function when the fine tune setting is Turbo mode (Register 0A bit 3) TURBO function sequence inverter. TURBO_INV=0: If TURBO value changes from 0 to 1, it will fine tune directly, Otherwise, it will delay 20ms to fine tune reference voltage. TURBO_INV=1: If TURBO value changes from 1 to 0, it will fine tune directly. Otherwise, it will delay 20ms to fine tune reference voltage 1 Reserved R/W 0 Reserved When register 09H bit 1 is set to FAULT_N mode, Set this bit to 1 to 0 FAULT_EN R/W 0 enable FAULT Function, When FAULT_N is low in S0 State, it will Shut down PWM_VRAM, PWM_VTT, LR_PCIE, LR_VID directly,. 2 TURBO_INV R/W 0 7.10 Bit PLED ACPI Frequency setting Register Index 0Ah Name R/W Default Description PLED frequency setting, When PLED_SET[9:8] set equal to S3_N, 7-6 PLED_SET[9:8] R/W 0 S5_N, the PLED pin will be tri-state (OD) *note : {1,1} represent S0 State, {1,0} represent S3 State, {00} represent S5 State, {01} the state is reserved 3 5-4 SLED_SET[9:8] R/W SLED frequency setting, When SLED_SET[9:8] set equal to S3_N, S5_N, the PLED pin will be tri-state (OD) *note : {1,1} represent S0 State, {1,0} represent S3 State, {00} represent S5 State, {01} the state is reserved 0 Manual mode or Turbo mode selection, 0:turbo 1:Manual If the setting is Turbo mode, set register 09H bit 3 to enable the fine tune 3 VFB_SEL R/W function. If the setting is Manual mode, Write Register 02/04/06/08 Bit [7:4] to fine tune voltage. 2 1 0 LED_INV VRAM_OCEN VTT_OCEN R/W R/W R/W 1 1 1 Set to 1 , the PLED and SLED CLK is inverted PWM_VRAM Over current enable PWM_VTT Over current enable 14 2007 V0.25P Fintek 7.11 Feature Integration Technology Inc. F72568 PLED ACPI Frequency setting Register Index 0Bh Bit Name R/W Default Description PLED frequency setting, When the PLED_SET[7:6] = S3_N, S5_N, PLED will be 1HZ toggle pulse with 50 duty cycle PLED_SET[5:4] = S3_N, S5_N, PLED will be 1/2 HZ toggle pulse with 7-0 PLED_SET[7:0] R/W 9B 50 duty cycle PLED_SET[3:2] = S3_N, S5_N, PLED will be 1/4HZ toggle pulse with 50 duty cycle PLED_SET[1:0] = S3_N, S5_N, PLED will drive low *note : {1,1} represent S0 State, {0,1} represents S3 State , {0,0} represent S5 State, {1,0} is tri-state , 7.12 Bit SLED ACPI Frequency setting Register Index 0Ch Name R/W Default Description SLED frequency setting, When the SLED_SET[7:6] = S3_N, S5_N, SLED will be 1HZ toggle pulse with 50 duty cycle SLED_SET[5:4] = S3_N, S5_N, SLED will be 1/2 HZ toggle pulse with 7-0 SLED_SET[7:0] R/W 98 50 duty cycle SLED_SET[3:2] = S3_N, S5_N, SLED will be 1/4HZ toggle pulse with 50 duty cycle SLED_SET[1:0] = S3_N, S5_N, SLED will drive low *note : {1,1} represent S0 State, {0,1} represents S3 State , {0,0} represent S5 State, {1,0} is tri-state , 7.13 Bit 7 6 5 4 Under Voltage, Over Current Enable Protection Register Index 10h Name VPCIE_UVEN VID_UVEN VDUAL3V_UVEN LR1_UVEN R/W R/W R/W R/W R/W Default 1 1 1 1 VPCIE Under voltage enable VID Under voltage enable Description VDUAL3V Under voltage enable LR1 Under voltage enable 15 2007 V0.25P Fintek 3 2 1 0 LR2_UVEN LR3_UVEN PWM_VTT_UVEN R/W R/W R/W 1 1 1 1 Feature Integration Technology Inc. F72568 LR2 Under voltage enable LR3 Under voltage enable PWM_VTT Under voltage enable PWM_VRAM Under voltage enable PWM_VRAM_UVEN R/W 7.14 Bit 7 6 5 4 3 2 Register Index 11h Name Reserved Reserved Reserved Reserved Reserved Reserved R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Function: when set to 1, it can decrease regulators VFB voltage, it must fix the related fine tune register bit2, bit 3 to zero, for example 100XX, It provide 4 kinds decrease voltage 1 DEC_VFB R/W 10000 : 0.72V 10001 : 0.70V 10010 : 0.68V 10011 : 0.66V 0 Set to 1 can toggle S5_N to recovery, if VRAM, VTT, LR_PCIE, LR_VID Shut down by Over current or Under voltage or Fault_N SD , Set to 0, must power off to recovery. 0 PROTECTION_SEL R/W 16 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 8 Electrical Characteristic Absolute Maximum Ratings PARAMETER IC supply voltage ESD classification Maximum junction temperature (plastic package) Maximum storage temperature Maximum lead temperature (soldering 10s) SYMBOL VCC HBM Tj TSTO RATINGS 7 2 - 0C to 125C -65~150 260 UNIT V kV C C C Note: If ICs are stressed beyond the limits listed in the "absolute maximum ratings", they may be permanently destroyed. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. DC and AC electrical characteristics (VCC = 12V, TA = 25C) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VCC SUPPLY CURRENT/Regulated Voltage Nominal supply current 5VCC POWER-ON RESET Rising VCC threshold Falling VCC threshold OSCILLATOR AND Soft-start Free running frequency Ramp Amplitude Soft-start interval Dead time REFERENCE VOLTAGE Reference voltage PWM CONTROLLER GATE DRIVERS Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink RUGATE RUGATE RLGATE RLGATE VDS = 1V, VGS = 12V, VDS = 1V, VGS = 12V VDS = 1V, VGS = 12V VDS = 1V, VGS = 12V 7 5 7 5 14 10 14 10 VREF VCC=5V, T= 25 0.784 0.8 0.816 V FOSC VOSC TSS TDT Css=0.1u 2V to 2V 8.4 20 200 250 1.5 12.4 30 17.4 50 300 kHz VP-P ms ns 3.0 2.7 3.3 3.0 3.6 3.3 V V ICC UGATE, LGATE and DRIVE2 open 6 15 mA 17 2007 V0.25P Fintek PARAMETER Error Amplifier Slew Rate DC Gain Linear Regulator DC Gain Gain Bandwidth Product Slew Rate Drive High Output Voltage Drive Low Output Voltage Drive High Output Source Current Drive Low Output Sink Current Protection OCSET Current Source FB Under Voltage Trip VRAM(VDDQ) UV Level VTT_PWM (VGMCH) UV Level Charge Pump Charge Pump Frequency Charge Pump Voltage Feature Integration Technology Inc. F72568 SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT SR A0 4.5 34 V/us dB 70 1.86 38 12 0 Vo=9V; VDDA=10V Vo=1V; VDDA=10V 0.52 -0.54 dB MHz V/us V V mA mA IOCSET FB Falling 0.4 0.4 0.4 40 0.5 0.5 0.5 0.6 0.6 0.6 uA V V V 250 9.5 KHz V Switch Controller DUALGATE Output High Voltage 9.5 10.8 10.8 12 12 13.2 13.2 V V V VCCGATE Output High Voltage USBGATE SS Source Current : Design Guarantee 9 Ordering Information Part Number F72568DG Package Type 48-LQFP Green Package Production Flow Commercial, 0C to +70C 18 2007 V0.25P Fintek Feature Integration Technology Inc. F72568 10 Package Dimensions (48LQFP) HD D 36 25 Dimension in inch Dimension in mm Min. --0.05 1.35 0.17 0.09 Symbol Min. Nom. Max. Nom. ----1.40 0.20 --7.00 7.00 0.50 9.00 9.00 Max. 1.60 0.15 1.45 0.27 0.20 37 24 E HE 48 13 1 e b 12 A A1 A2 b c D E e HD HE L L1 y 0 Notes: c 0.45 0.60 1.00 0.75 --0 0.08 3.5 --7 A2 A Seating Plane See Detail F A1 y L L1 Detail F 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. Feature Integration Technology Inc. Headquarters 3F-7, No 36, Tai Yuan St., Chupei City, Hsinchu, Taiwan 302, R.O.C. TEL : 886-3-5600168 FAX : 886-3-5600166 www: http://www.fintek.com.tw Taipei Office Bldg. K4, 7F, No.700, Chung Cheng Rd., Chungho City, Taipei, Taiwan 235, R.O.C. TEL : 866-2-8227-8027 FAX : 866-2-8227-8037 Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner 19 2007 V0.25P Fintek 11 Application Circuit Feature Integration Technology Inc. F72568 DUAL5V VRAM_PWM CONTROL VTT_PWM CONTROL ATX Power Connector VSB5V -5V -12V U1 R2 4.7k PS_ON# PS_ON# 11 12 13 14 15 16 17 18 19 20 3.3V 3.3V -12V 3.3V COM COM PS_ON 5V COM COM COM 5V COM COM -5V PWR_OK 5V 5VSB 5V 12V ATX 1 2 3 4 5 6 7 8 9 10 VCC3V VCC5VVSB5V VCC5V VCC12V L1 1.2uH C5 1500uF C6 1500uF C7 4.7uF C8 0.1uF VRAM_UGATE C9 470uF R24 3.9k VTT_PWM PWROK VTT_FB C15 10uF C18 470uF VTT_COMP R11 10.7K C16 C17 1.2n 47n R12 3.9k C10 0.1uF R3 2 Q2 L4 Q4 4.7u C12 470uF*3 VRAM_OPS VTT_PWR VTT_PWR for 1.25V R6 2 VRAM_LGATE R4 2 R1 2 Q3 R5 20k Q1 L3 4.7u L2 1.2uH C1 C2 C3 1500uF1500uF4.7uF C4 0.1uF VRAM_PWR VRAM_PWR for 1.8V C30 0.1uF 1 2 3 4 U2 UGATE PHASE BOOT PVCC PWM VCC GND LGATE 6612 R7 8 7 6 5 PWM_GND R8 10 C14 47n 2.7K C11 470uF 10 C13 47n VCC12V R9 3.4k VRAM_FB R10 R13 2.2K PWM_GND VTT_OPS R14 20k C19 10uF VCC12V VSB5V R15 10 VSB5V VRAM_PWR PCIE_PWR VPCIE_PWR for 1.5V VPCIE_DRV VPCIE_SEN R17 200 R18 220 Q5 PCIE_PWR C20 0.1uF D1 VCC_PWM C21 1uF D2 VPCIE_SEN VPCIE_DRV LR1_DRV LR1_SEN C22 LR2_SEN LR2_DRV LR3_DRV 1uF C24 1000uF U3 DUAL3V VCC12V DUAL POWER VDUAL3V_DRV VDUAL3V_SEN VSB5V VCC3V VCCGATE Q6 Q7 DUAL3V C29 1000uF R21 10k RSMRST# PWOK VDUAL3V_SEN VDUAL3V_DRV VCC3V VCCGATE USBGATE R19 DUALGATE 4.7k R20 4.7k VBAT VPCIE_SEN VPCIE_DRV LR1_DRV LR1_SEN VSB5V C1 GND C2 CP LR2_SEN LR2_DRV LR3_DRV 36 35 34 33 32 31 30 29 28 27 26 25 VCC3V R23 4.7k VCC5V VCC3V R25 4.7k PWROK PS_ON# SLP_S5# PLED SLED C25 C26 0.1uF 0.1uF F72568DG PWOKIN PS_ONIN# S5# SCLK SDATA PLED SLED VREF VID_GD VSB5V VTT_PWM VTT_FB TURBO# R22 FAULT# 3.9k 37 38 39 40 41 42 43 44 45 46 47 48 VDUAL3V_SEN VDUAL3V_DRV VCCGATE USBGATE DUALGATE GND RSMRST# VBAT PWOK VCC3V TURBO# FAULT# F72568DG LR3_SEN SS VID_SEN VID_DRV VTT_OPS GND VRAM_UGATE VRAM_LGATE VCC_PWM VRAM_OPS VRAM_FB VTT_COMP 24 23 22 21 20 19 18 17 16 15 14 13 LR3_SEN VID_SEN VID_DRV VTT_OPS VRAM_UGATE VRAM_LGATE VCC_PWM VRAM_OPS VRAM_FB VTT_COMP C27 0.1uF C28 0.1uF Q8 VID_PWR MOSFET N R28 100 R30 200 C32 1000uF VID POWER PCIE_PWR 1 2 3 4 5 6 7 8 9 10 11 12 VSB5V VTT_FB VID_PWR R27 4.7k VID_GD VID_DRV VID_SEN R29 4.7k SCLK SDATA R26 4.7k VTT_PWM C31 1uF USB POWER USBGATE VSB5V VCC5V VCCGATE Q9 Q10 USB5V C34 220uF C42 1u C33 0.1uF USB5V default for STR LR3_PWR DUAL3V LR1_DRV Q13 LR3_PWR LR1_SEN R36 100 R38 330 VTT_PWR LR1_PWR LR1_PWR for 1.05V LR2_DRV LR1_PWR LR2_SEN C38 220uF R37 R R39 R DUAL3V VCC5V VSB5V LED CONTROL LR2_PWR Q11 Q12 LR2_PWR R33 330 R34 330 LR3_DRV LR3_SEN VSB5V VCC5V VCCGATE DUALGATE Q14 Q15 DUAL5V R40 R R41 R DUAL POWER C39 220uF D3 LED PLED D4 LED SLED C40 220uF This power can support standby power This power can support standby power C41 1000uF Title Size C Date: |